Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to field effect transistors (FET) including self-aligned source/drain contacts.
Background of Invention
A FET includes a source/drain region formed in or upon a wafer and a gate covering a channel region formed in or upon the wafer. A FET may be an nFET or a pFET and may be formed utilizing CMOS (Complementary metal-oxide-semiconductor) fabrication techniques. Further scaling of such CMOS techniques may require independently reducing source/drain contact resistances for nFETs and pFETs.